The present invention relates to filter circuits generally and, more particularly, to a circuit that filters noise from a signal on a dynamic time-domain basis.
A Phase Lock Loop (PLL) circuit can be used to provide frequency domain filtering. However, PLLs generally consume a large amount of chip real estate, are difficult to design, and are process dependent. Additionally, frequency domain filtering is of limited use against high amplitude injected noise such as occurs in standard electrical fast transient burst (EFTB) tests.
The present invention concerns a circuit comprising a filter circuit and a delay circuit. The filter circuit may be configured to present an output signal in response to (i) an input signal having one or more glitches and (ii) a control signal having a plurality of transitions between a first and a second state. The delay circuit may be configured to generate the control signal such that the output signal is generated without glitches. In one example the delay circuit may dynamically adjust the control signal in response to a period of the input signal.
The objects, features and advantages of the present invention include providing a filtering circuit that may (i) operate independently of process variations, (ii) be ported to various technologies without significant redesign, (iii) use a minimum of chip real estate, (iv) provide a high degree of noise filtering, (v) provide filtering in the time domain, (vi) provide a minimum pulse width output despite a noisy input, and (vii) implement a delay that may be optimized to maximize the effectiveness of the filtering.